1. Field of invention
Depositing material in trenches formed in integrated circuit substrates, and in particular reducing the thickness variations of a silicon dioxide layer deposited in narrow and wide substrate trenches using a high density plasma chemical vapor deposition process.
2. Related art
In a typical integrated circuit, electrically active areas are formed in a semiconductor substrate. The active areas are separated by electrical insulation regions. One method of forming such insulation regions is shallow trench isolation (STI).
In a typical STI process, a silicon nitride layer is deposited over a monocrystalline silicon substrate. One or more other layers (e.g., polycrystalline silicon) may exist between the silicon nitride and the substrate. The silicon nitride layer is patterned to cover the active areas, but not the areas in which the insulation regions are to be formed. Trenches are etched in the substrate (and in overlying layers, if any) at insulation region locations. Then, an insulating layer of silicon dioxide (SiO2) is deposited. The silicon dioxide covers the silicon nitride and fills the trenches. Next, chemical-mechanical polishing (CMP) is used to remove the deposited silicon dioxide overlying the silicon nitride. The CMP stops at the silicon nitride, and the trenches remain filled with silicon dioxide. Finally, an etch (e.g., wet anisotropic etch using hydrofluoric acid) is performed.
A High Density Plasma Chemical Vapor Deposition (HDP-CVD) process is used to deposit the SiO2 in the trenches. The HDP-CVD process differs from Plasma Enhanced Chemical Vapor Deposition (PECVD) and low pressure Chemical Vapor Deposition (CVD). In HDP-CVD, the ion flux to the substrate surface on which material is deposited is larger than the net deposition flux to the surface. As a result, the deposited SiO2 film is more dense and has less hydrogen incorporation as compared to an SiO2 film deposited using PECVD. In addition, the HDP-CVD ion flux assists sputtering and oxide etch at the upper trench corners. A low pressure Chemical Vapor Deposition (CVD) process must be done in a furnace at high temperatures (typically above 700° C.) to thermally deposit SiO2 on the substrate. In contrast, HDP-CVD requires plasma to break down the gas species so that their components will form SiO2 on the substrate surface.
Isolation trenches may be characterized by an aspect ratio, which is the ratio of trench depth to trench width (depth divided by width). HDP-CVD is used for sub-micron ultra large scale integration (ULSI) technologies due to its high aspect ratio (more than 4:1) trench fill capability as compared with, for example, a low pressure CVD process.
A SPEED model tool, manufactured by NOVELLUS, Inc. of San Jose, Calif., can be used to deposit silicon dioxide in an HDP-CVD STI process. The substrate on which the silicon dioxide is to be deposited is placed in the tool's reaction chamber. A mixture of silane (SiH4), oxygen (O2), and inert (e.g., argon (Ar) or helium (He)) gasses is introduced into the reaction chamber. The silane and oxygen react to form silicon dioxide and hydrogen.
When a plasma (glow discharge) is formed in the reaction chamber, the HDP-CVD process deposits material. In many instances the HDP-CVD process also sputter etches at least a part of the deposited material. A low frequency (e.g., 400 kilohertz (kHz)) radio frequency (RF) signal is established between an electrode and the substrate and creates the plasma ions. In addition, a high frequency (HF) (e.g., 13.56 MegaHertz (MHz)) bias signal is established between the electrode and the substrate. The HF bias signal attracts positive ions (e.g., He+ ions) used to resputter oxide deposited at the top corners (cusps) of the trenches, and the resputtered oxide helps to fill the trench. The ion current results in a DC potential between the electrode (anode) and the substrate (cathode).
For trenches of equal depth, a wide trench's volume to be filled with oxide is larger than a narrow trench's volume to be filled. The amount of oxide etched from the top corners of the wide and narrow trenches is not proportional to the volumes to be filled. Therefore, relatively more etched oxide helps to fill the narrow trench than helps to fill the wide trench. As a result, when an HDP-CVD process ends, the oxide layer filling and overlying the narrow trench is thicker than the oxide layer filling and overlying the wide trench. During subsequent CMP, more oxide is removed over the wide trench than is removed over the narrow trench due to CMP overpolishing (“dishing”). The following hydrofluoric acid anisotropic etch does not promote uniform SiO2 thickness among the narrow and wide trenches. Accordingly, after HDP-CVD, CMP, and subsequent wet etch, the oxide thickness filling narrow and wide trenches is non-uniform. However, the SiO2 often serves as a base for subsequently deposited overlying layers. Since such overlying layers should be planar and have uniform thickness, it is desirable to deposit silicon dioxide such that the oxide thickness filling and overlying trenches of various aspect ratios on the same wafer is relatively uniform.